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EL2004 EL2004C
EL2004 EL2004C
350 MHz FET Buffer
Features
Slew rate 2500 V ms Rise time 1 ns Bandwidth 350 MHz ELH0033 pin compatible g5 to g15V operation 100 mA output current MIL-STD-883B Rev C devices manufactured in U S A
General Description
The EL2004 is a very high-speed FET input buffer line driver designed for unity gain applications at both high current (up to 100 mA) and at frequencies up to 350 MHz The 2500 V ms slew rate and wide bandwidth ensures the stability of the circuit when the EL2004 is used inside op amp feedback loops Applications for the EL2004 include line drivers video buffers wideband instrumentation and high-speed drivers for inductive and capacitive loads The performance of the EL2004 makes it an ideal buffer for video applications including input buffers for flash A D converters and output buffers for video DACs Its excellent phase linearity is particularly advantageous in digital signal processing applications Elantec facilities comply with MIL-I-45208A and are MILSTD-1772 certified Elantec's Military devices comply with MIL-STD-883B Revision C and are manufactured in our rigidly controlled ultra-clean facilities in Milpitas California For additional information on Elantec's Quality and Reliability Assurance Policy and procedures request brochure QRA-1
Applications
Coaxial cable driver Fast op amp booster Flash converter driver Video line driver High-speed sample and hold Pulse transformer driver A T E pin driver
Ordering Information
Part No EL2004CG EL2004G EL2004L Temp Range
b 25 C to a 85 C b 55 C to a 125 C
Package Outline TO-8 TO-8 MDP0002 MDP0002
Simplified Schematic
b 55 C to a 125 C 52-Pad LCC MDP0013
EL2004L MIL b 55 C to a 125 C 52-Pad LCC MDP0013
5962-89659 is the SMD version of this device
Connection Diagram
Case is Electrically Isolated
November 1993 Rev G
2004 - 1
Top View
2004 - 3
Note All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication however this data sheet cannot be a ``controlled document'' Current revisions if any to these specifications are maintained at the factory and are available upon your request We recommend checking the revision level before finalization of your design documentation Patent pending
1989 Elantec Inc
EL2004 EL2004C
350 MHz FET Buffer
Absolute Maximum Ratings (TA e 25 C)
VS VIN PD IOC IOP Supply Voltage (V a b Vb) Input Voltage Power Dissipation (See curves) Continuous Output Current Peak Output Current 40V 40V 1 5W g100 mA g250 mA TA Operating Temperature Range EL2004 EL2004C Operating Junction Temperature Storage Temperature Lead Temperature (Soldering 10 seconds)
b 55 C to a 125 C b 25 C to a 85 C
TJ TST
175 C
b 65 C to a 150 C
300 C
Important Note All parameters having Min Max specifications are guaranteed The Test Level column indicates the specific device testing actually performed during production and Quality inspection Elantec performs most electrical tests using modern high-speed automatic test equipment specifically the LTX77 Series system Unless otherwise noted all tests are pulsed tests therefore TJ e TC e TA Test Level I II III IV V Test Procedure 100% production tested and QA sample tested per QA test plan QCX0002 100% production tested at TA e 25 C and QA sample tested at TA e 25 C TMAX and TMIN per QA test plan QCX0002 QA sample tested per QA test plan QCX0002 Parameter is guaranteed (but not tested) by Design and Characterization Data Parameter is typical value at TA e 25 C for information purposes only
g15V DC Electrical Characteristics
VS e g15V TMIN k TA k TMAX VIN e 0V RL e 1 kX unless otherwise specified (Note 1) EL2004 Parameter Description Test Conditions Min VOS Output Offset Voltage Voltage Gain RS s 100 kX TJ e 25 C RS s 100 kX VIN e g10V RL e 100X VIN e g10V RIN ROUT VO Input Impedance Output Impedance Output Voltage Swing TJ e 25 C VIN e g1V VIN e g1 VDC DRL e 100X to Infinity VIN e g14V VIN e g10 5V RL e 100X TA e 25 C TJ e 25 C (Note 2) TA e 25 C (Note 3) TJ e TA e TMAX VIN e b10V IS Supply Current 20 20 24
g12
EL2004C Test Level I I I I I 0 96 0 90 108 0 98 0 95 1011 4
g12 g13 g9 8
Typ 5
Max 10 15
Min
Typ 12
Max 20 25 10 0 98
Test Level I III II II I
Units
mV mV VV VV X X V V nA nA TD is 3 2in nA nA mA
AV
0 97 0 92 108
0 98 0 95 1011 4
g13 g9 8
10 0 98
8
I I I
10
II II I
g9
g9
IIN
Input Current
0 25 25 10
I IV I V I 20 20
20 20 50
I IV III V
24
II
2
EL2004 EL2004C
350 MHz FET Buffer
g5V DC Electrical Characteristics
VS e g5V TMIN k TA k TMAX VIN e 0V RL e 50X unless otherwise specified EL2004 Parameter Description Test Conditions Min VOS Output Offset Voltage Voltage Gain RS s 100 kX TJ e 25 C RS s 100 kX VIN e g1V RL e 1 kX VIN e g1V RIN ROUT VO IIN Input Impedance Output Impedance Output Voltage Swing Input Current TJ e 25 C VIN e g1V VIN e g1 VDC DRL e 50X to Infinity VIN e g4V TJ e 25 C (Note 2) TA e 25 C (Note 3) TJ e TA e TMAX PSRR IS Power Supply Rejection Ratio Supply Current VS e g5V to g15V RL e 1 kX RL e 1 kX 60 17 5 20
g2 0
EL2004C Test Level I I I I I 0 90 0 80 1010 0 95 0 88 1011 4
g2 0 g2 9
Typ 10
Max 30 35
Min
Typ 10
Max 30 35 10 0 95
Test Level I III II II I
Units
mV mV VV VV X X V pA nA nA dB mA TD is 3 2in TD is 1 3in
AV
0 90 0 80 108
0 95 0 88 1011 4
g2 9
10 0 95
8
I I
10
II III
250 25 10
I IV I V I 60 17 5
500 5 20
I IV III V
20
II
Note 1 When operating at elevated temperatures the power dissipation of the EL2004 must be limited to the values shown in the typical performance curve ``Maximum Power Dissipation vs Temperature'' Junction to case thermal resistance is 31 C W when dissipation is spread among the transistors in a normal AC steady-state condition In special conditions where heat is concentrated in one output device junction temperature should be calculated using a thermal resistance of 70 C W Note 2 Specification is at 25 C junction temperature due to requirements of high-speed automatic testing Actual values at operating temperatures will exceed the value at TJ e 25 C When supply voltages are g15V no-load operating junction temperatures may rise 40 C to 60 C above ambient and more under load conditions Accordingly VOS may change one to several mV and IIN will change significantly during warm-up Refer to IIN vs Temperature graph for expected values Note 3 Measured in still air seven minutes after application of power See graph of Input Current During Warm-up for further information Note 4 Bandwidth is calculated from the rise time The EL2004 has a single pole gain and phase response up to the b3 dB frequency Note 5 Slew rate is measured between VOUT e a 2 5V and b2 5V for this test Note 6 Slew rate is measured between VOUT e a 1V and b1V for this test Pulse repetition rate is k50 MHz
g15V AC Electrical Characteristics
VS e g15V RL e 1 kX RS e 50X TJ e 25 C unless otherwise specified EL2004 Parameter Description Test Conditions Min BW Bandwidth (Note 4) RL e 50X ts Cin Settling Time to 1% Input Capacitance DVIN e 1V tr e 3 ns 200 140 Typ 350 200 6 3 Max Test Level I I V V Min 200 140 EL2004C Typ 350 200 6 3 Max Test Level I I V V Units
MHz MHz ns pF
3
EL2004 EL2004C
350 MHz FET Buffer
g15V AC Electrical Characteristics
VS e g15V RL e 1 kX RS e 50X TJ e 25 C unless otherwise specified
Contd
EL2004 EL2004C
Parameter
Description
Test Conditions
Test Test Units Min Typ Max Min Typ Max Level Level 2000 2500 1200 10 17 10 4 40 40 17 25 20 I V I I I V V V 2000 2500 1200 10 17 10 4 40 40 17 25 20 I V I I I V V V V ms V ms ns ns ns X dB dB
SR
Slew Rate
VIN e g5V (Note 5) CL e 100 pF VIN e g5V (Note 5)
tr
Rise Time DVIN P 0 6V Note See Test Figure DVIN P 0 6V RL e 50X Propagation Delay DVIN P 0 6V Note See Test Figure Output Impedance Power Supply Rejection Ratio Power Supply Rejection Ratio f e 1 MHz VIN e 1 VRMS DRL e 100X to Infinity DVS a e g1 5 Vpeak f e 1 kHz DVSb e g1 5 Vpeak f e 1 kHz
tp ROUT
a PSRR
b PSRR
g5V AC Electrical Characteristics
VS e g5V RL e 50X RS e 50X TJ e 25 C unless otherwise specified EL2004 Parameter Description Test Conditions EL2004C
Test Test Units Min Typ Max Min Typ Max Level Level 175 125 220 150 8 3 I IV V V I V 20 28 24 I IV I V V V 900 175 125 220 150 8 3 1200 500 16 23 12 4 30 30 20 28 24 I IV V V I V I IV I V V V MHz MHz ns pF V ms V ms ns ns ns X dB dB
BW
Bandwidth
RL e 1 kX (Note 4)
ts Cin SR
Settling Time to 1% Input Capacitance Slew Rate
DVIN e 1V tr e 3 ns
VIN e g2V (Note 6) CL e 100 pF VIN e g2V RL e 1 kX (Note 6)
900
1200 500 16 23 12 4 30 30
tr
Rise Time RL e 1 kX DVIN P 0 6V Note See Test Figure RL e 50X DVIN P 0 6V Propagation Delay RL e 1 kX DVIN P 0 6V Note See Test Figure Output Impedance Power Supply Rejection Ratio Power Supply Rejection Ratio f e 1 MHz VIN e 1 VRMS DRL e 100X to Infinity DVSb e g0 5 Vpeak f e 1 kHz DVS a e g0 5 Vpeak f e 1 kHz
tp ROUT
a PSRR
b PSRR
4
TD is 3 4in
TD is 2 7in
EL2004 EL2004C
350 MHz FET Buffer
AC Test Circuit
2004 - 4
Typical Performance Curves
TO-8 Maximum Power Dissipation
2004 - 5
Gain vs Input Voltage
Output Resistance vs Output Current
2004 - 7
5
EL2004 EL2004C
350 MHz FET Buffer
Typical Performance Curves
Rise Time vs Temperature
Contd
Small Signal Pulse Response Large Signal Pulse Response
Frequency Response
Offset Voltage vs Supply Voltage
Normalized Input Bias Current During Warm-up
Supply Current vs Supply Voltage
Output Voltage vs Supply Voltage
2004 - 8
6
EL2004 EL2004C
350 MHz FET Buffer
Applications Information
The EL2004 is one member of a family of high performance buffers manufactured by Elantec The 2004 is optimized for speed while others offer choices of input DC parameters or output drive or cost The following table illustrates those members available at the time of this printing Consult the factory for the latest capabilities in this developing line
Elantec's Buffer Family
Part ELH0002 ELH0033 EL2004 EL2005 Slew Rate V ms 200 1500 2500 1500 Bandwidth MHz 50 100 350 140 Input Current (Warm) 6 mA 2 5 nA 2 5 nA 0 1 nA Peak IOUT mA 400 250 250 250 Rise Time ns 7 29 10 25
Input Bias Current vs Temperature
Input Bias Current vs Input Voltage
Recommended Layout Precautions
The very high-speed performance of the EL2004 can only be realized by taking certain precautions in circuit layout and power supply decoupling Low inductance ceramic chip or disc power supply decoupling capacitors of 0 1 mF or more should be connected with the shortest practical lead lengths between the device supply leads and a ground plane In addition it can be helpful to parallel these with 4 7 mF electrolytics (Tantalum preferred) Failure to follow these precautions can result in oscillation
2004 - 9
In applications such as sample and hold circuits where it is important to maintain low input bias current over input voltage range the EL2005 High Accuracy Fast Buffer is recommended The input capacitance of EL2004 comprises the FET device gate-to-source capacitance (which is a function of input voltage) and stray capacitance to the case Effective input capacitance can be minimized by connecting the case to the output since it is electrically isolated Or for reduced radiation the case may be grounded The AC characteristics specified in this data sheet were obtained with the case floating
Circuit Operation
The EL2004 is effectively an ideal unity gain amplifier with almost infinite input impedance and about 6X output impedance
Input Characteristics
The input impedance of a junction FET is a strong function of temperature and input voltage Nominal input resistance of EL2004 is 1012 at 25 C junction but as IB doubles every 11 C in the JFET the input resistance falls During warm-up self-heating raises the junction temperature up to 60 C or more (without heatsink) so operating IB will be much higher than the data sheet 25 C specification Another factor which can increase bias current is input voltage If the input voltage is more than 20V below the positive supply the input current rises exponentially (See Curve )
7
Offset Voltage Adjustment
The EL2004's offset voltages have been actively laser trimmed at g15V supplies to meet specified limits when the offset adjust pin is shorted to the offset preset pin If external offset null is required the offset adjust pin should be connected to a 200X trim pot connected to the negative supply
EL2004 EL2004C
350 MHz FET Buffer
Circuit Operation
Contd
Current Limiting Using Current Sources
Offset Zero Adjust
2004 - 10
Capacitive Loading
The EL2004 is designed to drive capacitive loads up to several thousand picofarads without oscillation However peak current resulting from charging currents on fast edges should be limited below the absolute maximum peak current rating of 250 mA In some cases it may be necessary to employ one of the current limit schemes shown below
2004 - 12
Short Circuit Protection
Dynamic response of the EL2004 was preserved by excluding current limit circuits which are not needed in most applications However in situations where operating conditions are not controlled short circuit protection can be added by inserting resistors between the output device collectors and supplies as illustrated
Using Resistor Current Limiting
The inclusion of limiting resistors in the collectors of the output devices will reduce the output voltage swing and speed Decoupling VC a and VC b pins with capacitors to ground will retain full output swing for transient pulses An alternate active current limit technique that retains full DC output swing is shown above Here the current sources are saturated during normal operation thus applying full supply voltage to the VC pins Under fault conditions the voltage decreases as the current source reaches its limit RLIM e VBE 0 6V e e 6X ISC 100 mA
Power Supplies
The EL2004 has been characterized for both g15 and g5V dual supply operation but other combinations can also be useful For example in many video applications it is only necessary for the output to swing g2V or less but speed and distortion are important In this situation the input stage can be operated at the full g15V supply while the output collectors are returned to g5V The speed and distortion will be almost as good as if the whole circuit was operating at g15V but the dissipation is substantially reduced and higher load currents can be safely accommodated
2004 - 11
Suitable resistor values can be calculated as follows RSC e Va Vb e ISC ISC
8
where ISC s 100 mA for EL2004
EL2004 EL2004C
350 MHz FET Buffer
Circuit Operation
Contd
General Application Suggestions
Video DAC Buffer
Many of the available video D to A converters are unable to directly drive 50X or 75X cables The EL2004's excellent phase linearity at video frequencies make it an ideal solution In critical applications or where line termination is not controlled a matching pad should be used as shown The capacitor should be adjusted for optimum pulse response If properly layed out this circuit will not overshoot
Video DAC Buffer
Increasing Operating Voltage and Reducing Thermal Tail
When driving heavy loads the changing dissipation in the output transistors can sometimes cause temperature gradients in the circuit which cause a shift in offset voltage and the phenomenon known as ``thermal tail'' Bootstrapping the output as illustrated substantially reduces the power in the output transistors and mitigates the effect
High Voltage Inputs can be Accommodated with Bootstrapped Supplies
2004 - 14
Impedance Matching
The EL2004 provides power gain and isolation between source and load when used as an active tap or impedance matching device as illustrated here In this example there is no output matching pad between the 2004 and the 75X line Such matching is not needed when the distant end of the cable is properly terminated as there is no reflected signal to worry about and the 2004 isolates the source This technique allows the full output voltage of the EL2004 to be applied to the load
Impedance Converter
2004 - 13
Hardware
In order to utilize the full drive capabilities of the EL2004 it should be mounted with a heatsink particularly for extended temperature operation Suitable heatsinks include Thermalloy 2240A (33 C W) Wakefield 215CB (30 C W) and IERC-UP-TO-848CB (15 C W) The case is isolated from the circuit and may be connected to system chassis Sockets are not recommended as they add substantial inductance and capacitance which impair the performance of the device However for test purposes they are unavoidable and precautions such as shielding input from output are suggested
2004 - 15
9
EL2004 EL2004C
350 MHz FET Buffer
General Application Suggestions
Contd
Inverting Amplifier for 20 MHz Flash Converter
2004 - 16
Boosting the Output
Unlike most integrated cicuits two or more EL2004's can be paralleled for increased output drive This capability results from the finite output resistance and low output mismatch of the
EL2004 For example a 50X cable driver with g10V capability can be made by using two EL2004's A short-circuit protected version is shown below
50X Cable Driver with Short Circuit Protection
NPN e 2N6551 PNP e 2N6554
( 2W devices
or equivalent
2004 - 17
10
EL2004 EL2004C
350 MHz FET Buffer
Burn-In Circuit
2004 - 18
Pin numbers are for TO-8 package LCC uses the same schematic
11
EL2004 EL2004C
350 MHz FET Buffer
EL2004 Macromodel
Connections input
TAB WIDE
l l l l l l
Va
l l l l l
Vc a
l l l l
Vb
l l l
Vcb
l l
output
l
subckt M2004 5 12 1 10 9 11 Models model qn npn (is e 5eb14 bf e 150 vaf e 100 rc e 1 rb e 5 re e 1 ikf e 200mA a cje e 5pF cjc e 5pF mje e 42 mjc e 23 tf e 3nS tr e 200nS br e 5 vtf e 0) model qp pnp (is e 5eb14 bf e 150 vaf e 100 rc e 2 rb e 3 re e 1 ikf e 100mA a cje e 5 7pF cjc e 4pF tf e 3nS mje e 32 mjc e 43 tr e 170nS br e 5 vtf e 0) model qf njf (vto eb3V beta e 4 0eb3 cgd e 4pF cgs e 10pF lambda e 671 0eb6) Resistors r1 20 21 58 33 r2 27 10 58 33 r3 22 11 2 r4 11 23 2 Transistors j1 12 5 20 qf j4 24 10 26 qf q2 21 21 25 qn q3 24 24 25 qp q5 1 21 22 qn q6 9 24 23 qp q7 26 26 27 qn ends
12
TD is 3 8in
EL2004 EL2004C
350 MHz FET Buffer
EL2004 Macromodel
Contd
2004 - 19
13
BLANK
14
BLANK
15
EL2004 EL2004C
EL2004 EL2004C
350 MHz FET Buffer
General Disclaimer
Specifications contained in this data sheet are in effect as of the publication date shown Elantec Inc reserves the right to make changes in the circuitry or specifications contained herein at any time without notice Elantec Inc assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement
WARNING
Life Support Policy
November 1993 Rev G
Elantec Inc 1996 Tarob Court Milpitas CA 95035 Telephone (408) 945-1323 (800) 333-6314 Fax (408) 945-9305 European Office 44-71-482-4596
16
Elantec Inc products are not authorized for and should not be used within Life Support Systems without the specific written consent of Elantec Inc Life Support systems are equipment intended to support or sustain life and whose failure to perform when properly used in accordance with instructions provided can be reasonably expected to result in significant personal injury or death Users contemplating application of Elantec Inc products in Life Support Systems are requested to contact Elantec Inc factory headquarters to establish suitable terms conditions for these applications Elantec Inc 's warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages
Printed in U S A

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